In a simple sample-and-hold circuit a sampling switch momentarily connects one side of a holding capacitor to a signal voltage level. The other side of the capacitor is connected to a reference potential, typically ground potential. This stored signal voltage may then be used as an input to other circuits as desired. Naturally, it is desirable that the stored voltage accurately reflect the actual signal voltage. A significant problem arises when the circuit is implemented with MOS devices, since MOS transistors which are used as the sampling switch are known to introduce an error charge feedthrough as they open up. One way to reduce this effect has been to use the MOS devices in parallel complementary pairs, so that the feedthrough charges are largely canceled. The input signal is supplied to the switch through an operational amplifier. A feedback loop connected to the stored signal node of the storage capacitor via a buffer loops back to the inverting input of the operational amplifier, thereby forming what is commonly referred to as a "feedback sample-and-hold circuit."
When sample-and-hold circuits are used as stages in a transversal filter bank, the accuracy with which each stage stores the signal voltage becomes especially critical. Variations among the stages results in a fixed pattern noise in the output signal from the bank which is very difficult, if not impossible, to remove by filtering. Further improvements in the accuracy have been gained by the use of a switched secondary feedback correction network. Dual feedback circuits of this type are described, for example, in copending application Ser. No. 426,293, entitled "Switched Capacitor Feedback Sample-and-hold Circuit", filed Sept. 29, 1982 now abandoned in favor of a continuation application, Ser. No. 662,245, filed Oct. 18, 1984, and application Ser. No. 451,026, entitled "Switched Capacitor Feedback Sample-and-Hold Circuit", filed Dec. 20, 1982, which are assigned to the same assignee as is the present invention.
There remains a problem which relates to spurious stacking faults which sometimes appear to varying degrees in the switching devices. Such faults appearing in the sampling switch devices lead to unpredictable leakage of charge from the holding capacitor to the substrate. Reducing the size of the switch devices to reduce the leakage is not an option, since they are already small to minimize the effects of parasitic capacitances. Nor is it feasible to simply increase the value of the storage capacitor, because this capacitor is part of the primary feedback loop and cannot be increased without rendering the loop unstable.